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TitleDigital demodulator implementation parameters evaluated by simulation
Publication TypeJournal Article
Year of Publication1998
AuthorsHeald, Andrew B., Scott Neil L., and Vaughan Rodney G.
JournalConference Record / IEEE Global Telecommunications Conference
Volume2
Pagination1303 - 1308
Date Published1998
KeywordsBit error rate, Computer graphics, computer simulation, Demodulators, Digital communication systems, Digital demodulators, Digital signal processing, Error analysis, Frequency shift keying, Signal receivers, Synchronization, Synchronization timing error
AbstractThe performance of DSP receivers for digital communications is evaluated by computer simulation. The modulation is fast frequency shift keying. The confidence levels for the BER estimates are described and the parameters of interest are presented graphically. The effect of quantizer resolution, sample rate, signal level and synchronization timing error are quantified. The approach allows guidelines for the DSP designer who must otherwise implement a receiver within the constraints of a system design which typically compromises power consumption and component cost.
URLhttp://www.scopus.com/inward/record.url?eid=2-s2.0-0032269819&partnerID=40&md5=ab8105ad3c9b80dc2f4ae8b884aa95df

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